Some CMOS integrated circuits may be made in a partially depleted silicon on insulator (SOI) process. Certain applications such as electronics for satellites, upper rocket stages, space probes, spaceships, and other applications with radiation-hardened requirements impose special demands such as single event upset (SEU) mitigation, or mitigating electronic state upsets by single radiation-induced events, that are not met by circuit architecture for ordinary consumer electronics. SEU in space is caused by energetic particles traversing circuit nodes and depositing charge sufficient to disrupt operation.
Space applications typically call for random access memory (RAM) with high performance and low power requirements, as well as protection against radiation effects. Radiation can cause many undesirable effects in circuit operation. For example, radiation can change the conductance of MOS transistors by changing the threshold voltage (Vt). Ir space, heavy particles from a single cosmic ray are capable of depositing relatively large amounts of deposited charge on a circuit node. There is a direct relationship between the radiation induced upset rate requirements and the performance requirement of radiation hardened static random access memory (SRAM). Radiation can also generate significant levels of transient voltage and current disturbances on internal nodes, including power and ground.
These internal disturbances can slow circuit performance or even upset circuit operation, e.g., changing the state of a memory cell. For a given node within a memory cell, there exists an amount of deposited charge which the driving transistor and the nodal capacitance cannot absorb without failing to maintain the node in the desired state. Therefore, the radiation induced charge can result in a change in the stored data state. Some specialized circuit architecture technologies have used designs such as back-ta-back reverse-biased Schottky resistors as compact high value resistors with an active delay element (ADE) in SRAM cells.